Skip to main content
Verilator is a static analysis tool for Verilog and SystemVerilog hardware designs.

​
Files

Verilator runs on changed files with the following extensions:
  • .v
  • .sv

​
Configuration

Verilator is enabled by default. Disable it by setting reviews.tools.verilator.enabled: false in your .coderabbit.yaml. Findings appear inline with Verilator rule identifiers, affected line ranges, and severity.

​
When we skip Verilator

CodeRabbit skips Verilator when:
  • The pull request has no changed .v or .sv files.
  • reviews.tools.verilator.enabled is set to false.
  • An existing Verilator invocation is detected in the repository’s GitHub Actions workflows.